Voltages or currents may be manipulated in resistor networks under digital control if switches are used to vary the connectivity of the resistors. When configured with digital control, the network can be considered a DAC (Digital to Analog Converter) since it commonly results in an analog output parameter proportional to the digital number applied, or sometimes a Multiplying DAC (MDAC) in cases where a conversion scale factor is involved.
Certain classes of such networks of resistors and switches are known to contain the fewest number of elements, and the smallest dynamic range of values. One member of this optimum class is the commonly used R-2R network. There are two distinct ways that R-2R networks can be connected to make a DAC: the so called “voltage mode DAC” and “current mode DAC”. Each has its advantages and disadvantages, discussed in the paper by Walt Kester, available online at http://www.analog.com/static/imported-files/tutorials/MT-015.pdf.
Of interest in the present case is the ability of multiple MDAC's to form a sum-of-products as is often required in signal processing and other applications. Since a voltage mode MDAC has constant output impedance, multiples MDACs may be connected to a common output node and the sum-of-products will appear as the voltage on that output node. However such sum-of-products configurations have limitations.
In a sum-of-products using voltage mode R-2R MDACs, the expression for the output is:
  Y  =            1      N        ·                  ∑                  i          =          0                          N          -          1                    ⁢                          ⁢                        X          i                ·                  D          i                    where X is the analog input voltage, D the digital number applied and N the total number of MDACs used.
While such an approach is practical for some applications, the presence of zero or near-zero values in the D variable can significantly attenuate the output signal. This arises because the addition of each MDAC with Di=0 will have no effect on the summation (Xi*Di=0), but it will reduce the output signal since the addition of an MDAC has increased N to N+1 and the output signal is a function of 1/N. For example, if the Di are {0.8, 0.5, 0.7, 0.6, 0.9, 0.7, 0.8, 0.6, 0.7, 0.8} and all Xi are equal to one, the output will be 0.71. However if Di are {0.08, 0.05, 0.07, 0.06, 0.9, 0.07, 0.08, 0.06, 0.07, 0.08}, i.e. each being scaled down by 10 except the 0.9 near the middle, then we have not 0.71 but only 0.152. Clearly, as more elements with values near to zero are added there is an increased attenuation in the output signal.
This limits the applicability of the voltage mode R-2R MDAC to those sum-of-product applications that do not have many near zero-values. Unfortunately, one of the more interesting sum-of-products applications is the finite impulse response filter (FIR) in which the coefficients are almost all near zero. This limits the usefulness of the R-2R MDAC implementation despite the attraction it has of a small number of resistor values.
There is therefore a need for a device capable of producing a weighted sum of input values that does not suffer from an increased attenuation when there are many near zero coefficients, but that operates with a limited dynamic range of resistor or impedance values.
These and other objects of the invention will be better understood by reference to the detailed description of the preferred embodiment which follows. Note that not all of the objects are necessarily met by all embodiments of the invention described below or by the invention defined by each of the claims.